Центральноазиатский журнал академических исследований 2-jild 8-son (2024) · 8–18-betlar

IMPLEMENTATION OF 4 BIT SYNCHRONOUS SEQUENTIAL UP/DOWN COUNTER USING JKFF AND 7-SEGMENT DISPLAY.

Xatamov, Javohirbek

DOI: 10.5281/zenodo.13375178 · Manbada o'qish → · PDF (manba serverida)

Annotatsiya

This paper presents the design and implementation of a 4-bit synchronous sequential up/down counter using JK flip-flops. The counter operates in both ascending and descending modes, displaying output on two 7-segment displays. The design process includes state diagram creation, JK state table derivation, and Boolean expression optimization using Karnaugh maps. Implemented in Logisim, the final circuit demonstrates a functional counter capable of displaying hexadecimal values from 0 to F. This work illustrates the effective use of JK flip-flops in synchronous counter design for digital applications.

Digital counter, synchronous counter, circuit design, karnaugh maps, Logisim, sequential logic.

Metadata manbasi: jurnal OAI-PMH arxivi · Sindex to'liq matnni saqlamaydi, manbaga havola beradi.